1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a thin film transistor substrate of a horizontal electric field type and a fabricating method thereof that can reduce the number of mask processes.
2. Discussion of the Related Art
Generally, liquid crystal displays (LCDs) control the light transmittance of liquid crystal using an electric field to display pictures. LCDs are largely classified into a vertical electric field type and a horizontal electric field type, depending upon the direction of the electric field driving the liquid crystal.
An LCD of the vertical electric field type drives a liquid crystal in a twisted nematic (TN) mode with a vertical electric field formed between a pixel electrode on a lower substrate and a common electrode on a upper substrate, with the pixel and common electrodes facing each other. Such an LCD of the vertical electric field type has an advantage of a high aperture ratio, while having a drawback of a narrow viewing angle of about 90°. An LCD of the horizontal electric field type drives a liquid crystal in an in plane switch (IPS) mode with a horizontal electric field between a pixel electrode and a common electrode on a lower substrate, which are arranged in parallel to each other. Such an LCD of the horizontal electric field type has an advantage of a wide viewing angle of about 160°.
Hereinafter, an LCD of the horizontal electric field type will be described in detail. An LCD of a horizontal electric field type includes a thin film transistor substrate (i.e., a lower substrate) and a color filter substrate (i.e., an upper substrate) attached to and facing each other. The LCD further includes a spacer for uniformly maintaining a cell gap between the two substrates and a liquid crystal filled into the cell gap. The thin film transistor substrate includes a plurality of signal wirings for forming a horizontal electric field for each pixel, a plurality of thin film transistors, and an alignment film coated thereon to align the liquid crystal. The color filter substrate includes a color filter for implementing a color, a black matrix for preventing a light leakage and an alignment film coated thereon to align the liquid crystal.
In such a liquid crystal display, completing the thin film transistor substrate requires a complicated fabrication process with several mask processes, leading to an increased manufacturing cost. In order to solve this problem, active researches are in progress to reduce the number of the mask processes in completing the thin film transistor substrate. This is because one mask process includes many sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, a four-mask process has been developed. This four-mask process reduces one mask process from the existent five-mask process that was a standard mask process in manufacturing the thin film transistor substrate.
FIG. 1 is a plan view illustrating a structure of a thin film transistor substrate of a horizontal electric type fabricated by a four-mask process according to a related art, and FIG. 2 is sectional views of the thin film transistor substrate taken along the lines I-I′ and II-II′ in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 45 in such a manner to cross each other with a gate insulating film 46 therebetween, a thin film transistor 6 provided near each crossing, a pixel electrode 14 and a common electrode 18 provided at a pixel area defined by the gate line 2 and the data line 4 for forming a horizontal electric field, and a common line 16 connected to the common electrode 18. Further, the thin film transistor substrate includes a storage capacitor 20 provided at an overlapping portion between the pixel electrode 14 and the common line 16, a gate pad 24 connected to the gate line 2, and a data pad 30 connected to the data line 4 and a common pad 36 connected to the common line 16. The gate line 2 supplied with a gate signal and the data line 4 supplied with a data signal define the pixel area, with the gate insulating film therebetween 46. The common line 16 supplied with a reference voltage for driving the liquid crystal is provided in parallel to the gate line 2 within the pixel area.
The thin film transistor 6 charges the data signal of the data line 4 to the pixel electrode 14 in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 14. The thin film transistor 6 further includes an active layer 48 overlapping the gate electrode 8 with a gate insulating film 46 therebetween to define a channel between the source electrode 10 and the drain electrode 12. The active layer 48 also overlaps the data line 4, a lower data pad electrode 32 and an upper storage electrode 22. On the active layer 48 is an ohmic contact layer 50 to form an ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, and the lower data pad electrode 32.
The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 13 passing through a protective film 52, and is provided at the pixel area. More specifically, the pixel electrode 14 includes a first horizontal part 14A connected to the drain electrode 12 and provided in parallel with adjacent gate lines 2, a second horizontal part 14B overlapping the common line 16, and a finger part 14C provided in parallel between the first and second horizontal parts 14A and 14B. The common electrode 18 is connected to the common line 16 and is provided at the pixel area. More specially, the common electrode 18 is provided in parallel with the finger part 14C of the pixel electrode 14 at the pixel area.
Accordingly, a horizontal electric field is formed between the pixel electrode 14 to which a data signal is applied via the thin film transistor 6 and the common electrode 18 to which a reference voltage is applied via the common line 16. More specifically, a horizontal electric field is formed between the finger part 14C of the pixel electrode 14 and the common electrode 18. Liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate rotate by such a horizontal electric field due to a dielectric anisotropy of the liquid crystal molecules. Transmittance of the pixel area is differentiated depending upon an extent of the rotation of the liquid crystal molecules, thereby implementing gray scale levels.
The storage capacitor 20 is constructed with the common line 16, an upper storage electrode 22 overlapping the common line 16, the gate insulating film 46, the active layer 48 and the ohmic contact layer 50, as shown in FIG. 2. The gate insulating film 46, the active layer 48 and the ohmic contact layer 50 are sandwiched between the common line 16 and the upper storage electrode 22. In the storage capacitor 20, the pixel electrode 14 is connected to the upper storage electrode 22 via a second contact hole 21 passing through the protective film 52. The storage capacitor 20 maintains a data signal charged in the pixel electrode 14 until the next data signal is charged.
The gate line 2 is connected to a gate driver (not shown) via the gate pad 24. The gate pad 24 is constructed with a lower gate pad electrode 26 extended from the gate line 2, and an upper gate pad electrode 28 connected to the lower gate pad electrode 26 via a third contact hole 27 passing through the gate insulating film 46 and the protective film 52. The data line 4 is connected to the data driver (not shown) via the data pad 30. The data pad 30 is constructed with a lower data pad electrode 32 extended from the data line 4, and an upper data pad electrode 34 connected to the lower data pad electrode 32 via a fourth contact hole 33 passing through the protective film 52. The common line 16 receives a reference voltage from an external reference voltage source (not shown) through the common pad 36. The common pad 36 is constructed with a lower common pad electrode 38 extended from the common line 16, and an upper common pad electrode 40 connected to the lower common pad electrode 38 via a fifth contact hole 39 passing through the gate insulating film 46 and the protective film 52.
A method of fabricating the thin film transistor substrate having the above-mentioned structure by a four-mask process will be described in detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a gate metal pattern group (or a first conductive pattern group) including the gate line 2, the gate electrode 8 and the lower gate pad electrode 26, the common line 16, the common electrode 18 and the lower common pad electrode 38 is provided on the lower substrate 45 by a first mask process. More specifically, a gate metal layer (or a first conductive layer) is formed on the lower substrate 45 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography and etching processes using a first mask to thereby form the gate metal pattern group including the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common line 16, common electrode 18 and the lower common pad electrode 38. Herein, the gate metal layer is formed of metal such as aluminum-group metal, chrome (Cr) or molybdenum (Mo).
Referring to FIG. 3B, the gate insulating film 46 is deposited onto the lower substrate 45 provided with the gate metal pattern group. Further, a semiconductor pattern including the active layer 48 and the ohmic contact layer 50 and a source/drain metal pattern group (or a second conductive pattern group) including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32 and the upper storage electrode 22 are formed on the gate insulating film 46 by a second mask process. More specifically, the gate insulating film 46, an amorphous silicon layer, an n+ amorphous silicon layer and a source/drain metal layer (or a second conductive layer) are sequentially deposited on the lower substrate 45 provided with the gate metal pattern group by such deposition techniques as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 46 is formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal layer is formed of molybdenum (Mo), titanium (Ti), tantalum (Ta) or molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by a photolithography process using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing the photo-resist pattern at the channel portion to have a lower height than other source/drain pattern portions. Subsequently, the source/drain metal layer is patterned by a wet-etching process using the photo-resist pattern to thereby form the source/drain metal pattern group including the data line 4, the source electrode 10, the drain electrode 12 which is integral to the source electrode 10 and the upper storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry-etching process using the same photo-resist pattern to thereby form the ohmic contact layer 50 and the active layer 48. The photo-resist pattern having a relatively low height at the channel portion is removed by an ashing process, and thereafter the source/drain metal pattern and the ohmic contact layer 50 at the channel portion are etched by a dry-etching process. Thus, the active layer 48 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12. Then, the photo-resist pattern left on the source/drain metal pattern group is removed by a stripping process.
Referring to FIG. 3C, the protective film 52 including the first to fifth contact holes 13, 21, 27, 33 and 39 are formed on the gate insulating film 46 provided with the source/drain metal pattern group by a third mask process. More specifically, the protective film 52 is entirely deposited on the gate insulating film 46 provided with the source/drain metal pattern group by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). The protective film 52 is patterned by photolithography and etching processes using a third mask to thereby define the first to fifth contact holes 13, 21, 27, 33 and 39. The first contact hole 13 passes through the protective film 52 to expose the drain electrode 12, whereas the second contact hole 21 passes through the protective film 52 to expose the upper storage electrode 22. The third contact hole 27 passes through the protective film 52 and the gate insulating film 46 to expose the lower gate pad electrode 26. The fourth contact hole 32 passes through the protective film 52 to expose the lower data pad electrode 32. The fifth contact hole 30 passes through the protective film 52 and the gate insulating film 48 to expose the lower common pad electrode 38. Herein, when the source/drain metal layer is formed of a metal material having a large dry-etching ratio such as molybdenum (Mo), then each of the first, second and fourth contact holes 13, 21 and 33 passes through the drain electrode 12, the upper storage electrode 22 and the lower data pad electrode 32 to thereby expose the side surfaces thereof. The protective film 50 is formed of an inorganic material identical to the gate insulating film 46, or an organic material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, a transparent conductive film pattern group (or a third conductive pattern group) including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40 are formed on the protective film 52 by a fourth mask process. More specifically, a transparent conductive film (or a third conductive layer) is deposited onto the protective film 52 by a deposition technique such as sputtering, etc. Then, the transparent conductive film is patterned by photolithography and etching processes using a fourth mask to thereby provide the transparent conductive pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40. The pixel electrode 14 is electrically connected to the drain electrode 12 via the first contact hole 13, and is also electrically connected to the upper storage electrode 22 via the second contact hole 21. The upper gate pad electrode 28 is electrically connected to the lower gate pad electrode 26 via the third contact hole 37. The upper data pad electrode 34 is electrically connected to the lower data pad electrode 32 via the fourth contact hole 33. The upper common pad electrode 40 is electrically connected to the lower common pad electrode 38 via the fifth contact hole 39. Herein, the transparent conductive film is formed of indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO), or the like.
The thin film transistor substrate of a horizontal electric field type and the fabricating method thereof as described above employs a four-mask process, thereby reducing the number of fabricating processes and reducing the manufacturing cost in comparison with such thin film transistor substrates fabricated by a five-mask process. However, because such a four-mask process still requires a complicate fabricating process and has a limit in cost reduction, a more simplified fabricating process would be beneficial to reduce the manufacturing cost.